Triple Modular Redundancy System Research Articles

Estimation of the parameters of triple modular redundancy system under step partially accelerated life tests using Frechet distribution

Triple modular redundancy system (TMR) is repetition of important components or functions of the system. It aims to increase the reliability and reducing the failure rate. This study is focused on the estimating of the distribution’s parameters of the "TMR system" under the partly life test with gradual stress, as it included every component in the system that follows The Frechete distribution. This research aimed to analysis the reliability of this triple modular system. The optimal time for stress change was determined using two criteria according to the accelerated stress strategy under the new distribution, as well as estimating the reliability of the system by using the maximum likelihood (MLE) method. The efficiency of the " MLE" in estimate the parameters of the new distribution is one of the most important conclusions in this study. Therefore, the design of the "TMR” system can have a lengthy lifetime and higher safety, reducing the risks of unexpected failure and the economic losses.

Performance Evaluation of Tilt-based Vehicle Accident Report System Using Triple Modular Redundancy

A vehicle accident report system was designed to detect accidents accurately and send message to related person. However, after accident, some components or modules can be damaged and it may cause failure of accident detection. Therefore, Triple Modular Redundancy (TMR) method was implemented in the system to mask faults within the modules and ensure the system to continue working. TMR is one of passive hardware redundancy methods. The system includes three MPU-6050 sensors functioning as vehicle tilt sensors to provide hardware redundancy, a TC9548A module serving as an I2C multiplexer, an Arduino Nano acting as a microcontroller and voter, and a NodeMCU ESP8266 responsible for transmitting message. Based on experiment results, the TMR system has a reliability value of 0.9928, a failure rate value of 0.0004/cycle, and accuracy of 3 sensor value of 85%. While, the non-redundancy system has a reliability value of 0.9286, a failure rate value of 0.0053/cycle, and accuracy of single sensor value of 57%. The results of the system process were sent to and displayed via an e-mail. It can be concluded that the TMR system has better performance than the non-redundancy one.

Reliability analysis of the triple modular redundancy system under step-partially accelerated life tests using Lomax distribution

Triple modular redundancy (TMR) is a robust technique utilized in safety-critical applications to enhance fault-tolerance and reliability. This article focuses on estimating the distribution parameters of a TMR system under step-stress partially accelerated life tests, where each component included in the system follows a Lomax distribution. The study aims to analyze the system’s reliability and mean residual lifetime based on the estimated parameters. Various estimation techniques, including maximum likelihood, percentile, least squares, and maximum product of spacings, are explored. Additionally, the optimal stress change time is determined using two criteria. An illustrative example supported by two actual data sets is presented to showcase the methodology’s application. By conducting Monte Carlo simulations, the assessment of the estimation methods’ effectiveness reveals that the maximum likelihood method outperforms the other three methods in terms of both accuracy and performance, as indicated by the numerical outcomes. This research contributes to the understanding and practical implementation of TMR systems in safety-critical industries, potentially saving lives and preventing catastrophic events.

Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs

FPGAs are the most prominent electronic devices used in space, military, and commercial applications. This is because of the reprogrammable feature in FPGAs. The electronic and computational components are sensitive to various types of events caused by ionisation effects. The problem at hand is effectively addressed by a fault-tolerant method known as Triple Modular Redundancy (TMR). Triple Modular Redundancy (TMR) has been demonstrated as an effective and dependable technique for mitigating the impacts of single-event upsets (SEUs) and single-event transients (SETs). However, to ensure effective mitigation of SETs, an additional delay element is required. However, the implementation of a TMR system may incur higher costs due to the requirement for additional hardware resources. Subsequently, numerous studies have focused on conventional fault-tolerant techniques with the aim of reducing the hardware overhead associated with TMR, although these efforts have not yielded satisfactory results. In order to tackle this issue more effectively, this paper introduces a novel error analysis approach. This approach works based on the error percentage algorithm and also proposes the other method, a preferential method for reducing the overhead of the hardware in existing fault-tolerant techniques. The proposed work is applied to the multiplier circuit to analyse its efficiency. The proposed work reduces the hardware resources by 48% when compared with the existing work.

X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework for Error-Tolerant Applications Deployed in Critical Systems

Triple modular redundancy (TMR) is one of the most common techniques in fault-tolerant systems, in which the output is determined by a majority voter. However, the design diversity of replicated modules and/or soft errors that are more likely to happen in the nanoscale era may affect the majority voting scheme. Besides, the significant overheads of the TMR scheme may limit its usage in energy consumption and area-constrained critical systems. However, for most inherently error-resilient applications such as image processing and vision deployed in critical systems (such as autonomous vehicles and robotics), achieving a given level of reliability has more priority than precise results. Therefore, these applications can benefit from the approximate computing paradigm to achieve higher energy efficiency and a lower area. This article proposes an energy-efficient approximate reliability (X-Rel) framework to overcome the aforementioned challenges of the TMR systems and get the full potential of approximate computing without sacrificing the desired reliability constraint and output quality. The X-Rel framework relies on relaxing the precision of the voter based on a systematical error bounding method that leverages user-defined quality and reliability constraints. Afterward, the size of the achieved voter is used to approximate the TMR modules such that the overall area and energy consumption are minimized. The effectiveness of employing the proposed X-Rel technique in a TMR structure, for different quality constraints as well as with various reliability bounds, is evaluated in a 15-nm FinFET technology. The results of the X-Rel voter show delay, area, and energy consumption reductions of up to 86%, 87%, and 98%, respectively, when compared to those of the state-of-the-art approximate TMR voters. Also, the effectiveness of the proposed X-Rel-based TMR structure is assessed in four benchmark applications from different domains. For these benchmarks, the results show 1.59 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> , 2.35 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> , and 3.39 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> energy-delay-area-product (EDAP) reduction for less than 1%, 5%, and 10% output quality degradations, respectively. Finally, an image processing application is benchmarked to evaluate the X-Rel framework efficacy in the presence of errors, where the results show up to a 4.78 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> higher output image quality in comparison with the typical TMR voters.

Implementation of Voter by using Artificial Bee Colony Algorithm for Fault Tolerant System

In a fault tolerant system, voting algorithm plays a major role in decision making. Inexact majority voting, majority voting, and weighted voters are most popular voting algorithms. In each of these techniques, redundant modules produce unpredictable outputs, and finding an agreement among these outputs is the functionality of voter. In this proposed system, voter is implemented using soft computing technique called ABC algorithm. The basic ABC algorithm is a very modest, adaptable and clear model. There are two categories of searchers in the hive of ABC; namely, unemployed searchers and employed searchers. Based on the intelligent performance of honey bee swarm, ABC is one of the optimization algorithms. The behaviours of bees are used to optimize weights of Triple Modular Redundant system, where each module plays an imperative role in the selection of voter. For evaluating the performance of voting algorithms, some performance measures have been defined; they are, safety and availability measures. ABC algorithm has been proposed to improve the safety and availability of the existing system.

Resilience of Time Diversity Against Multiharmonic Electromagnetic Disturbances Under Reverberation Conditions: An Overview of Fault Mechanisms

In this article, time diversity is used as an electromagnetic resilience technique in a triple modular redundant (TMR) communication channel that is subjected to a multiharmonic electromagnetic disturbance under semireverberant environments. This study is carried out in light of new electromagnetic interference (EMI) condition monitoring definitions, which provide a better insight into the actual state of the system. An explanation of the different fault mechanisms based on the new definitions is provided for a time diverse TMR system with a two-out-of-three majority voter and is compared with the previously used EMI condition monitoring definitions. The new definitions provide a better understanding on how to interpret the results of an EMI detector or an EMI corrector by keeping in consideration the safety and availability aspects of system.

Effectiveness of Frequency Diversity to Create EM-Diversity in Triple-Modular Redundant Data Transmission Systems

This article investigates the effectiveness of frequency diversity, the usage of three different frequencies inside a triple modular redundant data transmission system, to cope with harsh electro-magnetic disturbances. Such a triple modular redundant system uses three different data channels to transmit data after which majority voting is applied to conclude one final output. Using a Monte-Carlo based simulation framework calculates the influence of harsh electromagnetic disturbances on the communication channel. The bit error rate and the amount of undetectable dangerous failures are calculated, and serve as a quality measure for our study. In addition, this article describes a semianalytical model that implements the critical factors that are necessary to get comparable results to the Monte-Carlo simulation framework, with less computational effort. To find the bit frequencies that optimize the bit error rate (BER), and minimize the amount of dangerous failures, a sweep is performed over two out of three data frequencies while fixing the third data frequency, and the electromagnetic interference (EMI) frequency. Notable relationships are recognized in the visual results and further studied. This results in six equations visualizing the relationships between the data and EMI frequencies. Finally, three equations predict the prospective BER, and undetectable failures, which is confirmed using the Monte-Carlo simulation framework.

Neutron Radiation Testing of a TMR VexRiscv Soft Processor on SRAM-Based FPGAs

Soft processors are often used within field-programmable gate array (FPGA) designs in radiation hazardous environments. These systems are susceptible to single-event upsets (SEUs) that can corrupt both the hardware configuration and software implementation. Mitigation of these SEUs can be accomplished by applying triple modular redundancy (TMR) techniques to the processor. This article presents fault injection and neutron radiation results of a Linux-capable TMR VexRiscv processor. The TMR processor achieved a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> improvement in SEU-induced mean fluence to failure with a cost of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> resource utilization. To further understand the TMR system failures, additional post-radiation fault injection was performed with targets generated from the radiation data. This analysis showed that not all the failures were due to single-bit upsets, but potentially caused by multibit upsets, nontriplicated IO, and unmonitored nonconfiguration RAM (CRAM) SEUs.

A Self-Checking TMR Voter for Increased Reliability Consensus Voting in FPGAs

Nanoscale field-programmable gate array (FPGA) circuits are more prone to radiation-induced effects in harsh environments because of their memory-based reconfigurable logic fabric. Consequently, for mission- or safety-critical applications, appropriate fault-tolerance techniques are widely employed. The most commonly applied technique for hardening FPGAs against radiation-induced upsets is triple modular redundancy (TMR). Voting circuits used in TMR implementations are decentralized and consensus is calculated from the redundant outputs off-chip. However, if there are an insufficient number of pins available on the chip carrier, the TMR system must be reduced to an on-chip unprotected simplex system, meaning voters used at those locations become single point of failure. In this paper, we propose a self-checking voting circuit for increased reliability consensus voting on FPGAs. Through fault injection and reliability analyses, we demonstrate that the proposed voter, which utilizes redundant voting copies, is approximately 26% more reliable than an unprotected simplex voter when reliability values of voters over normalized time are averaged.

Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery

Field-Programmable Gate Arrays (FPGAs) provide ideal platforms for meeting the computational requirements of future space-based processing systems. However, FPGAs are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for dynamically reconfiguring corrupted modules of Triple Modular Redundant(TMR) components are well known. However, most of these techniques utilize resources that are themselves susceptible to SEUs to transfer reconfiguration requests from the TMR voters to a central reconfiguration controller. This paper evaluates the impact of these Reconfiguration Control Networks (RCNs) on the system’s reliability and performance. We provide an overview of RCNs reported in the literature and compare them in terms of dependability, scalability and performance. Most importantly, we compare the performance of soft networks with that of a hard network that utilizes the Internal Configuration Access Port(ICAP) available in advanced Xilinx devices to periodically read the TMR voter states. We have implemented our designs on a Xilinx Artix-7 FPGA to assess the resulting resource utilization and performance as well as to evaluate their soft error vulnerability using analytical and fault injection techniques. Results show that, of the RCN topologies studied, the ICAP-based approach is the most reliable despite having the highest network latency. We also conclude that a module-based recovery approach is less reliable than scrubbing unless the RCN is implemented with redundancy and repaired when it suffers from configuration memory errors.

A Fault Tolerant Voter Circuit for Triple Modular Redundant System

Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability of the fault tolerant system. This paper provides simulation results and analysis of a fault tolerant voter circuit. In a Triple Modular Redundant (TMR) system, the robustness of the voter circuit has been improved. For this purpose, redundancy at transistor level has been added. In this technique each transistor of the various building blocks (Ex-OR gate, Multiplexer) of the voter circuit is replaced by a quadded-transistor structure. Quadded transistor structure provides built in immunity to all single defects as well as a large number of multiple defects. To evaluate the effectiveness of the voter circuit an IC layout in 90nm CMOS technology is developed. FPNI layout using qNAND hypercell is also designed and analysed. By simulation procedure it has been shown that the proposed fault tolerant voter circuit works properly as a majority voter in different faulty conditions of a TMR system. Moreover, it has been shown that in the presence of internal hardware failure (failure in transistor level) the voter circuit works properly.

Internet Protocol Based Satellite On-Board System

The reliability of satellite data communication can be enhanced by designing two subsystems involving data communication among subsystem and data communication between satellie and Ground Station (GS). In this paper, Error Control Coding (ECC) is applied in satellite data communication with Automatic Repeat Request (ARQ) method. Further, bit error checking uses the calculation of 15 bit Cyclic Redundancy Check (CRC) Controller Area Network (CAN) standard. The calculation of CRC is attached in CAN frame over IP communication protocol between primary OBC and secondary OBC. OBC is designed by implementing Triple Modular Redundant system on a Linux-based operating system. The CAN frame over IP simulation with manual input is found to correct all corrupted data. When the simulation uses NetEM, the system corrects 100 % data with 0-10 % value of corruption with maximum time transfer of 84.472 seconds. ION DTN is also found to correct all corrupted data with values from 0 to 2 % and maximum delay at an altitude of 50,000 kilometer orbit using NetEm for TMTC mission. The testing results show that the system will keep carrying out its mission as long as a fault does not occur on all three OBC at the same time.

Low power modular redundancy: a power efficient fault tolerant approach for digital circuits

Purpose To increase protection level against transient faults, circuit designers usually take advantage of redundant structures like Triple Modular Redundancy (TMR). Since redundancy compel a significant power overhead, proposing a low power fault tolerant technique in digital circuits is the main objective of this research work. Design/methodology/approach In order to moderate power consumption, we use a dual to triple modular redundancy. In fact, we put one of the modules in a TMR system in sleep mode while the other two operating modules are producing the same outputs. Once a mismatch is detected, the third one exits the sleep mode and the dual modular redundancy (DMR) approach turns into a conventional TMR. Also a novel stoppable clock generator is proposed to handle the sleep mode of the third module. Finally, a new three-input majority voter, compatible with our proposed technique, is presented. Findings Power analysis of combinational circuit benchmarks, ISCAS85, and ISCAS89 as sequential circuit benchmarks are depicted. Simulation results show the power reduction of up to 30% in comparison with the conventional modular redundancy approach. Originality/value Since modular redundancy is the most effective and the most well-known fault tolerant approach which is widely used in reliable circuits designs, it is important to reduce its power consumption. In this paper configuring the sleep mode operation of a circuit and stoppable clock generator lead to a new TMR technique in which the power consumption is strongly reduced.

An Incorporated Voting Strategy on Majority and Score- based Fuzzy Voting Algorithms for Safety-Critical Systems

Triple Modular Redundancy (TMR) is usually used to increase safety and the reliability of safety-critical systems where three identical segments are used in identical and the ultimate outcome is reached using voting techniques. Fault masking is one of the main techniques to improve the normal actions of a range of safety-critical techniques. Some commercial areas which implement such techniques include process control, transport, and atomic power place and army programs. Integrated Voter for majority and weighted-average used to provide for a fault masking capability in safety-critical systems [1]. The Majority voting gives a high level of safety and the weighted-average offers a good level of availability. If integrated these two gives a good level of safety in Majority voting not in integrated voting. Here propose a new voting algorithm for faulty masking taking the disadvantage of previous algorithm. In this Incorporating Majority voting and score based fuzzy voting schemes. Safety performance is evaluated by running proposed, Majority and score based fuzzy voting on a triple modular redundant (TMR) system for 10000 voting cycles in various error scenarios. Experimental results show that proposed fuzzy Voter is given a higher safety than other two voting algorithms.

Development of sensor nodes based on fault tolerance

In the present paper, and a fail-safe system capable of operating in safety side even upon occurrence of failures was designed where internet of things (IoTs)-based sensor nodes allowed fault tolerance based on hardware redundancy. The fault tolerance system masked faults with the application of triple modular redundancy (TMR) system and enabled fail-safe control by using a comparator for fault detection and self-diagnostics. The fault-tolerant sensor nodes presented in the paper were installed outdoors where disasters/calamities could occur and could execute the specified algorithms even upon occurrence of faults allowing the use in areas with poor environments and particularly the application to plant facilities for management of oil and gas pipelines, etc. as the high reliability could be guaranteed.

Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems

In this paper, we present a scan-chain-based multiple error recovery technique for triple modular redundancy (TMR) systems (SMERTMR). The proposed technique reuses scan-chain flip-flops fabricated for testability purposes to detect and correct faulty modules in the presence of single or multiple transient faults. In the proposed technique, the manifested errors are detected at the modules' outputs, while the latent faults are detected by comparing the internal states of the TMR modules. Upon detection of any mismatch, the faulty modules are located and the state of a fault-free module is copied into the faulty modules. In case of detecting a permanent fault, the system is degraded to a master/checker configuration by disregarding the faulty module. FPGA-based fault injection experiments reveal that SMERTMR has the error detection and recovery coverage of 100% and 99.7% in the presence of single and two faulty modules, respectively, while imposing negligible area and performance overheads on the traditional TMR systems.

On Analogue TMR System

This chapter presents a reliability model of the TMR (Triple Modular Redundancy) system based on analogue measurement channels. While reliability modelling of the standard TMR system (based on digital channels) has been well described in many previous publications, an applicable reliability solution for analogue measurement channels is still missing. First, the structure of analogue measurement channel is described in this chapter. Then, the reliability model of the wiring system is introduced. Next, the standard TMR model is presented and its reliability model is mentioned. An analogue TMR measurement channel system is introduced and its reliability model based on Markov processes is presented. Then the reliability model of the communication channel is described. Finally, the reliability of this model is analytically calculated and the solution is applied to an example.

Using Bayesian networks in reliability evaluation for subsea blowout preventer control system

The Bayesian network models of redundant systems including parallel system and voting system, taking account of common cause failure and imperfect coverage, are proposed. The Triple Modular Redundancy (TMR) and Double Dual Modular Redundancy (DDMR) control systems for subsea Blowout Preventer (BOP) are presented. By applying the proposed Bayesian network models, the reliability of subsea BOP control systems are evaluated at any given time, and the difference between posterior and prior probabilities of each single component given the system failure is obtained. The effects of coverage factor of redundant subsystem and failure rate of single component on reliability of systems are also researched. The results show that the DDMR control system has a little higher reliability than TMR system. To improve the reliability of subsea BOP control systems, the component failure rates of Ethernet switch (ES), programmable logic controller (PLC) and personal computer (PC) should be reduced for TMR system, whereas the failure rates of ES and PC should be reduced for DDMR system. The recovery mechanism of PLC, PC and ES subsystems, and PC and ES subsystems should be paid more attention for TMR and DDMR control systems, respectively.

A dependability model for TMR system

Much research has been done on the dependability evaluation of computer systems. However, much of this is gone no further than study of the fault coverage of such systems, with little focus on the relationship between fault coverage and overall system dependability. In this paper, a Markovian dependability model for triple-modular-redundancy (TMR) system is presented. Having fully considered the effects of fault coverage, working time, and constant failure rate of single module on the dependability of the target TMR system, the model is built based on the stepwise degradation strategy. Through the model, the relationship between the fault coverage and the dependability of the system is determined. What is more, the dependability of the system can be dynamically and precisely predicted at any given time with the fault coverage set. This will be of much benefit for the dependability evaluation and improvement, and be helpful for the system design and maintenance.